//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
//Date        : Wed Apr 20 13:37:39 2016
//Host        : WK116 running 64-bit major release  (build 9200)
//Command     : generate_target PmodHYGRO.bd
//Design      : PmodHYGRO
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module PmodHYGRO
   (AXI_LITE_IIC_araddr,
    AXI_LITE_IIC_arready,
    AXI_LITE_IIC_arvalid,
    AXI_LITE_IIC_awaddr,
    AXI_LITE_IIC_awready,
    AXI_LITE_IIC_awvalid,
    AXI_LITE_IIC_bready,
    AXI_LITE_IIC_bresp,
    AXI_LITE_IIC_bvalid,
    AXI_LITE_IIC_rdata,
    AXI_LITE_IIC_rready,
    AXI_LITE_IIC_rresp,
    AXI_LITE_IIC_rvalid,
    AXI_LITE_IIC_wdata,
    AXI_LITE_IIC_wready,
    AXI_LITE_IIC_wstrb,
    AXI_LITE_IIC_wvalid,
    
    AXI_LITE_TMR_araddr,
    AXI_LITE_TMR_arready,
    AXI_LITE_TMR_arvalid,
    AXI_LITE_TMR_awaddr,
    AXI_LITE_TMR_awready,
    AXI_LITE_TMR_awvalid,
    AXI_LITE_TMR_bready,
    AXI_LITE_TMR_bresp,
    AXI_LITE_TMR_bvalid,
    AXI_LITE_TMR_rdata,
    AXI_LITE_TMR_rready,
    AXI_LITE_TMR_rresp,
    AXI_LITE_TMR_rvalid,
    AXI_LITE_TMR_wdata,
    AXI_LITE_TMR_wready,
    AXI_LITE_TMR_wstrb,
    AXI_LITE_TMR_wvalid,
    
    I2C_Interrupt,
    
    Pmod_out_pin10_i,
    Pmod_out_pin10_o,
    Pmod_out_pin10_t,
    Pmod_out_pin1_i,
    Pmod_out_pin1_o,
    Pmod_out_pin1_t,
    Pmod_out_pin2_i,
    Pmod_out_pin2_o,
    Pmod_out_pin2_t,
    Pmod_out_pin3_i,
    Pmod_out_pin3_o,
    Pmod_out_pin3_t,
    Pmod_out_pin4_i,
    Pmod_out_pin4_o,
    Pmod_out_pin4_t,
    Pmod_out_pin7_i,
    Pmod_out_pin7_o,
    Pmod_out_pin7_t,
    Pmod_out_pin8_i,
    Pmod_out_pin8_o,
    Pmod_out_pin8_t,
    Pmod_out_pin9_i,
    Pmod_out_pin9_o,
    Pmod_out_pin9_t,
    
    s_axi_aclk,
    s_axi_aresetn
    );
    output I2C_Interrupt;
  
    input [8:0]   AXI_LITE_IIC_araddr;
    output        AXI_LITE_IIC_arready;
    input         AXI_LITE_IIC_arvalid;
    input [8:0]   AXI_LITE_IIC_awaddr;
    output        AXI_LITE_IIC_awready;
    input         AXI_LITE_IIC_awvalid;
    input         AXI_LITE_IIC_bready;
    output [1:0]  AXI_LITE_IIC_bresp;
    output        AXI_LITE_IIC_bvalid;
    output [31:0] AXI_LITE_IIC_rdata;
    input         AXI_LITE_IIC_rready;
    output [1:0]  AXI_LITE_IIC_rresp;
    output        AXI_LITE_IIC_rvalid;
    input [31:0]  AXI_LITE_IIC_wdata;
    output        AXI_LITE_IIC_wready;
    input [3:0]   AXI_LITE_IIC_wstrb;
    input         AXI_LITE_IIC_wvalid;
    
    input [8:0]   AXI_LITE_TMR_araddr;
    output        AXI_LITE_TMR_arready;
    input         AXI_LITE_TMR_arvalid;
    input [8:0]   AXI_LITE_TMR_awaddr;
    output        AXI_LITE_TMR_awready;
    input         AXI_LITE_TMR_awvalid;
    input         AXI_LITE_TMR_bready;
    output [1:0]  AXI_LITE_TMR_bresp;
    output        AXI_LITE_TMR_bvalid;
    output [31:0] AXI_LITE_TMR_rdata;
    input         AXI_LITE_TMR_rready;
    output [1:0]  AXI_LITE_TMR_rresp;
    output        AXI_LITE_TMR_rvalid;
    input [31:0]  AXI_LITE_TMR_wdata;
    output        AXI_LITE_TMR_wready;
    input [3:0]   AXI_LITE_TMR_wstrb;
    input         AXI_LITE_TMR_wvalid;
    
  input Pmod_out_pin10_i;
  output Pmod_out_pin10_o;
  output Pmod_out_pin10_t;
  input Pmod_out_pin1_i;
  output Pmod_out_pin1_o;
  output Pmod_out_pin1_t;
  input Pmod_out_pin2_i;
  output Pmod_out_pin2_o;
  output Pmod_out_pin2_t;
  input Pmod_out_pin3_i;
  output Pmod_out_pin3_o;
  output Pmod_out_pin3_t;
  input Pmod_out_pin4_i;
  output Pmod_out_pin4_o;
  output Pmod_out_pin4_t;
  input Pmod_out_pin7_i;
  output Pmod_out_pin7_o;
  output Pmod_out_pin7_t;
  input Pmod_out_pin8_i;
  output Pmod_out_pin8_o;
  output Pmod_out_pin8_t;
  input Pmod_out_pin9_i;
  output Pmod_out_pin9_o;
  output Pmod_out_pin9_t;
  input s_axi_aclk;
  input s_axi_aresetn;

    wire [8:0]    S_AXI_1_ARADDR;
    wire          S_AXI_1_ARREADY;
    wire          S_AXI_1_ARVALID;
    wire [8:0]    S_AXI_1_AWADDR;
    wire          S_AXI_1_AWREADY;
    wire          S_AXI_1_AWVALID;
    wire          S_AXI_1_BREADY;
    wire [1:0]    S_AXI_1_BRESP;
    wire          S_AXI_1_BVALID;
    wire [31:0]   S_AXI_1_RDATA;
    wire          S_AXI_1_RREADY;
    wire [1:0]    S_AXI_1_RRESP;
    wire          S_AXI_1_RVALID;
    wire [31:0]   S_AXI_1_WDATA;
    wire          S_AXI_1_WREADY;
    wire [3:0]    S_AXI_1_WSTRB;
    wire          S_AXI_1_WVALID;
  
    wire [8:0]    S_AXI_2_ARADDR;
    wire          S_AXI_2_ARREADY;
    wire          S_AXI_2_ARVALID;
    wire [8:0]    S_AXI_2_AWADDR;
    wire          S_AXI_2_AWREADY;
    wire          S_AXI_2_AWVALID;
    wire          S_AXI_2_BREADY;
    wire [1:0]    S_AXI_2_BRESP;
    wire          S_AXI_2_BVALID;
    wire [31:0]   S_AXI_2_RDATA;
    wire          S_AXI_2_RREADY;
    wire [1:0]    S_AXI_2_RRESP;
    wire          S_AXI_2_RVALID;
    wire [31:0]   S_AXI_2_WDATA;
    wire          S_AXI_2_WREADY;
    wire [3:0]    S_AXI_2_WSTRB;
    wire          S_AXI_2_WVALID;
    
  
  wire axi_iic_0_IIC_SCL_I;
  wire axi_iic_0_IIC_SCL_O;
  wire axi_iic_0_IIC_SCL_T;
  wire axi_iic_0_IIC_SDA_I;
  wire axi_iic_0_IIC_SDA_O;
  wire axi_iic_0_IIC_SDA_T;
  wire [1:0]axi_iic_0_gpo;
  wire axi_iic_0_iic2intc_irpt;
  
  wire pmod_bridge_0_Pmod_out_PIN10_I;
  wire pmod_bridge_0_Pmod_out_PIN10_O;
  wire pmod_bridge_0_Pmod_out_PIN10_T;
  wire pmod_bridge_0_Pmod_out_PIN1_I;
  wire pmod_bridge_0_Pmod_out_PIN1_O;
  wire pmod_bridge_0_Pmod_out_PIN1_T;
  wire pmod_bridge_0_Pmod_out_PIN2_I;
  wire pmod_bridge_0_Pmod_out_PIN2_O;
  wire pmod_bridge_0_Pmod_out_PIN2_T;
  wire pmod_bridge_0_Pmod_out_PIN3_I;
  wire pmod_bridge_0_Pmod_out_PIN3_O;
  wire pmod_bridge_0_Pmod_out_PIN3_T;
  wire pmod_bridge_0_Pmod_out_PIN4_I;
  wire pmod_bridge_0_Pmod_out_PIN4_O;
  wire pmod_bridge_0_Pmod_out_PIN4_T;
  wire pmod_bridge_0_Pmod_out_PIN7_I;
  wire pmod_bridge_0_Pmod_out_PIN7_O;
  wire pmod_bridge_0_Pmod_out_PIN7_T;
  wire pmod_bridge_0_Pmod_out_PIN8_I;
  wire pmod_bridge_0_Pmod_out_PIN8_O;
  wire pmod_bridge_0_Pmod_out_PIN8_T;
  wire pmod_bridge_0_Pmod_out_PIN9_I;
  wire pmod_bridge_0_Pmod_out_PIN9_O;
  wire pmod_bridge_0_Pmod_out_PIN9_T;
  
  wire s_axi_aclk_1;
  wire s_axi_aresetn_1;
  
  wire [1:0]xlconstant_0_dout;

    assign AXI_LITE_IIC_arready       = S_AXI_1_ARREADY;
    assign AXI_LITE_IIC_awready       = S_AXI_1_AWREADY;
    assign AXI_LITE_IIC_bresp[1:0]    = S_AXI_1_BRESP;
    assign AXI_LITE_IIC_bvalid        = S_AXI_1_BVALID;
    assign AXI_LITE_IIC_rdata[31:0]   = S_AXI_1_RDATA;
    assign AXI_LITE_IIC_rresp[1:0]    = S_AXI_1_RRESP;
    assign AXI_LITE_IIC_rvalid        = S_AXI_1_RVALID;
    assign AXI_LITE_IIC_wready        = S_AXI_1_WREADY;
    
    assign AXI_LITE_TMR_arready       = S_AXI_2_ARREADY;
    assign AXI_LITE_TMR_awready       = S_AXI_2_AWREADY;
    assign AXI_LITE_TMR_bresp[1:0]    = S_AXI_2_BRESP;
    assign AXI_LITE_TMR_bvalid        = S_AXI_2_BVALID;
    assign AXI_LITE_TMR_rdata[31:0]   = S_AXI_2_RDATA;
    assign AXI_LITE_TMR_rresp[1:0]    = S_AXI_2_RRESP;
    assign AXI_LITE_TMR_rvalid        = S_AXI_2_RVALID;
    assign AXI_LITE_TMR_wready        = S_AXI_2_WREADY;
    
  assign I2C_Interrupt = axi_iic_0_iic2intc_irpt;
  assign Pmod_out_pin10_o = pmod_bridge_0_Pmod_out_PIN10_O;
  assign Pmod_out_pin10_t = pmod_bridge_0_Pmod_out_PIN10_T;
  assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
  assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
  assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
  assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
  assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
  assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
  assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
  assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
  assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
  assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
  assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
  assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
  assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
  assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
  
    assign S_AXI_2_ARADDR     = AXI_LITE_TMR_araddr[8:0];
    assign S_AXI_2_ARVALID    = AXI_LITE_TMR_arvalid;
    assign S_AXI_2_AWADDR     = AXI_LITE_TMR_awaddr[8:0];
    assign S_AXI_2_AWVALID    = AXI_LITE_TMR_awvalid;
    assign S_AXI_2_BREADY     = AXI_LITE_TMR_bready;
    assign S_AXI_2_RREADY     = AXI_LITE_TMR_rready;
    assign S_AXI_2_WDATA      = AXI_LITE_TMR_wdata[31:0];
    assign S_AXI_2_WSTRB      = AXI_LITE_TMR_wstrb[3:0];
    assign S_AXI_2_WVALID     = AXI_LITE_TMR_wvalid;

    assign S_AXI_1_ARADDR     = AXI_LITE_IIC_araddr[8:0];
    assign S_AXI_1_ARVALID    = AXI_LITE_IIC_arvalid;
    assign S_AXI_1_AWADDR     = AXI_LITE_IIC_awaddr[8:0];
    assign S_AXI_1_AWVALID    = AXI_LITE_IIC_awvalid;
    assign S_AXI_1_BREADY     = AXI_LITE_IIC_bready;
    assign S_AXI_1_RREADY     = AXI_LITE_IIC_rready;
    assign S_AXI_1_WDATA      = AXI_LITE_IIC_wdata[31:0];
    assign S_AXI_1_WSTRB      = AXI_LITE_IIC_wstrb[3:0];
    assign S_AXI_1_WVALID     = AXI_LITE_IIC_wvalid;

  assign pmod_bridge_0_Pmod_out_PIN10_I = Pmod_out_pin10_i;
  assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
  assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
  assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
  assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
  assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
  assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
  assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
  
  assign s_axi_aclk_1 = s_axi_aclk;
  assign s_axi_aresetn_1 = s_axi_aresetn;
  
    PmodHYGRO_axi_timer_0_0 axi_timer_0 (
          .s_axi_aclk       (s_axi_aclk_1),
          .s_axi_araddr     (S_AXI_2_ARADDR),
          .s_axi_aresetn    (s_axi_aresetn_1),
          .s_axi_arready    (S_AXI_2_ARREADY),
          .s_axi_arvalid    (S_AXI_2_ARVALID),
          .s_axi_awaddr     (S_AXI_2_AWADDR),
          .s_axi_awready    (S_AXI_2_AWREADY),
          .s_axi_awvalid    (S_AXI_2_AWVALID),
          .s_axi_bready     (S_AXI_2_BREADY),
          .s_axi_bresp      (S_AXI_2_BRESP),
          .s_axi_bvalid     (S_AXI_2_BVALID),
          .s_axi_rdata      (S_AXI_2_RDATA),
          .s_axi_rready     (S_AXI_2_RREADY),
          .s_axi_rresp      (S_AXI_2_RRESP),
          .s_axi_rvalid     (S_AXI_2_RVALID),
          .s_axi_wdata      (S_AXI_2_WDATA),
          .s_axi_wready     (S_AXI_2_WREADY),
          .s_axi_wstrb      (S_AXI_2_WSTRB),
          .s_axi_wvalid     (S_AXI_2_WVALID)
    );
  PmodHYGRO_axi_iic_0_0 axi_iic_0
       (.gpo(axi_iic_0_gpo),
        .iic2intc_irpt(axi_iic_0_iic2intc_irpt),
        .s_axi_aclk(s_axi_aclk_1),
        .s_axi_araddr(S_AXI_1_ARADDR),
        .s_axi_aresetn(s_axi_aresetn_1),
        .s_axi_arready(S_AXI_1_ARREADY),
        .s_axi_arvalid(S_AXI_1_ARVALID),
        .s_axi_awaddr(S_AXI_1_AWADDR),
        .s_axi_awready(S_AXI_1_AWREADY),
        .s_axi_awvalid(S_AXI_1_AWVALID),
        .s_axi_bready(S_AXI_1_BREADY),
        .s_axi_bresp(S_AXI_1_BRESP),
        .s_axi_bvalid(S_AXI_1_BVALID),
        .s_axi_rdata(S_AXI_1_RDATA),
        .s_axi_rready(S_AXI_1_RREADY),
        .s_axi_rresp(S_AXI_1_RRESP),
        .s_axi_rvalid(S_AXI_1_RVALID),
        .s_axi_wdata(S_AXI_1_WDATA),
        .s_axi_wready(S_AXI_1_WREADY),
        .s_axi_wstrb(S_AXI_1_WSTRB),
        .s_axi_wvalid(S_AXI_1_WVALID),
        .scl_i(axi_iic_0_IIC_SCL_I),
        .scl_o(axi_iic_0_IIC_SCL_O),
        .scl_t(axi_iic_0_IIC_SCL_T),
        .sda_i(axi_iic_0_IIC_SDA_I),
        .sda_o(axi_iic_0_IIC_SDA_O),
        .sda_t(axi_iic_0_IIC_SDA_T));
  PmodHYGRO_pmod_bridge_0_0 pmod_bridge_0
       (.in2_I(axi_iic_0_IIC_SCL_I),
        .in2_O(axi_iic_0_IIC_SCL_O),
        .in2_T(axi_iic_0_IIC_SCL_T),
        .in3_I(axi_iic_0_IIC_SDA_I),
        .in3_O(axi_iic_0_IIC_SDA_O),
        .in3_T(axi_iic_0_IIC_SDA_T),
        .in_top_i2c_gpio_bus_O(axi_iic_0_gpo),
        .in_top_i2c_gpio_bus_T(xlconstant_0_dout),
        .out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
        .out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
        .out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
        .out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
        .out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
        .out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
        .out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
        .out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
        .out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
        .out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
        .out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
        .out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
        .out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
        .out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
        .out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
        .out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
        .out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
        .out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
        .out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
        .out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
        .out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
        .out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
        .out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
        .out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
  PmodHYGRO_xlconstant_0_0 xlconstant_0
       (.dout(xlconstant_0_dout));
endmodule
